Field of the Invention
The present invention relates to an image capturing device.
Description of the Related Art
As an analog-to-digital (AD) conversion scheme of converting an analog signal into a digital signal, (1) a successive approximation register AD conversion scheme, (2) a single-slope AD conversion scheme, (3) a cyclic AD conversion scheme, (4) a ΔΣAD conversion scheme, and so on are proposed.
In the publication of Japanese Unexamined Patent Application, First Publication No. 2013-70255 (hereinafter referred to as Patent Literature 1), a configuration of a cyclic AD conversion circuit capable of accurately estimating a value of an amplification degree β (1<β<2) is shown as a cyclic AD conversion circuit using a cyclic AD conversion scheme. FIG. 8 shows an example of AD conversion using the cyclic AD conversion circuit of Patent Literature 1. The analog signal Vin of the AD conversion target is a signal of a range of 0<Vin<Vfs. The cyclic AD conversion circuit has a comparator and generates a digital value (0 or 1) according to a comparison result by comparing an analog signal Vin with a threshold value Vth.
Because the analog signal Vin is less than the threshold value Vth, a digital value of 0 is generated. The cyclic AD conversion circuit amplifies the analog signal Vin by multiplying the analog signal Vin by an amplification degree β and further executes computation according to the digital value of 0 to output a residual signal Vres(1). The digital value of 0 generated by comparing the analog signal Vin with the threshold value Vth becomes a value of a most significant bit (MSB) of a digital value corresponding to the analog signal Vin.
Next, the cyclic AD conversion circuit performs a process similar to that described above on the residual signal Vres(1). Specifically, the cyclic AD conversion circuit compares the residual signal Vres(1) with the threshold value Vth. Because the residual signal Vres(1) is greater than the threshold value Vth, a digital value of 1 is generated. The cyclic AD conversion circuit amplifies the residual signal Vres(1) by multiplying the residual signal Vres(1) by the amplification degree β and further executes computation according to the digital value of 1 to output a residual signal Vres(2). The digital value of 1 generated by comparing the residual signal Vres(1) with the threshold value Vth becomes a value of the next bit of the MSB of the digital value corresponding to the analog signal Vin.
Next, the cyclic AD conversion circuit performs a process similar to that described above on the residual signal Vres(2) and generates a digital value of 0 and a residual signal Vres(3). Thereafter, the cyclic AD conversion circuit iterates a similar process to generate a digital value of a necessary number of bits and a residual signal. In FIG. 8, a state in which the residual signal Vres(3), the digital value of 0 corresponding to the residual signal Vres(3), a residual signal Vres(4), and the digital value of 1 corresponding to the residual signal Vres(4) are generated is shown.
Through the above-described process, the cyclic AD conversion circuit acquires a digital value sequence (01001). This digital value sequence is a base β digital value sequence having the amplification degree β as a base. Lastly, the cyclic AD conversion circuit converts the base β digital value sequence into a binary digital value sequence.
There is a problem in that degradation (for example, miscoding) of AD conversion precision occurs when a value of the amplification degree β deviates from a design value due to variation in manufacturing conditions, and so on. Thus, the cyclic AD conversion circuit of Patent Literature 1 accurately estimates the value of the amplification degree β and converts the base β digital value sequence into a binary digital value sequence using the estimated value of the amplification degree β.